Numerous integrated circuit devices, structures and techniques of fabricating same are known to the prior art. The following prior art patents and summaries are submitted to generally represent the state of the art.
Reference is made to U.S. Pat. No. 3,986,897 entitled "Aluminum Treatment to Prevent Hillocking" granted Oct. 19, 1976 to L. D. McMillan et al. The McMillan et al patent discloses a method of surface treating aluminum, particularly aluminum metallization for semiconductors, which includes subjecting the aluminum surface to be treated with fuming nitric acid for one to ten minutes at room temperature. Follow cleaning, the surface is subjected to boiling water for five to fifteen minutes. The foregoing treatment appears to form a boehmite [alO--(OH)] layer on the surface of the aluminum, thereby substantially eliminating hillocking.
Reference is made to U.S. Pat. No. 4,068,018 entitled "Process For Preparing A Mask For Use In Manufacturing A Semiconductor Device" granted Jan. 10, 1978 to T. Hashimoto et al. The Hashimoto et al patent discloses a process for preparing a mask, such as a photo-mask, used in a selective etching process in the manufacture of a semiconductor device or a mask for use in a process for selectively providing a porous layer of silicon or for anodic oxidation of a metal layer, in which ions accelerated at a predetermined voltage are implanted into a photoresist film to a predetermined dose level.
Reference is made to U.S. Pat. No. 4,089,709 entitled "Method for Passivating Aluminum Layers on Semiconductor Devices" granted May 16, 1978 to J. M. Harris. The Harris patent discloses an aluminum layer such as an intraconnect circuit semiconductor device passivated by oxidizing the aluminum layers to form a thin layer of amorphous alumina thereon. The alumina layer is coated with a surface active agent to form a hydrophobic surface on the aluminum oxide to inhibit the creation and growth of ALOOH on the oxide layer. The hydropholic surface is coated with a conventional passivating material such as silicon dioxide, epoxy or the like.
Reference is made to U.S. Pat. No. 4,157,269 entitled "Utilizing Polysilicon Diffusion Sources and Special Masking Techniques" granted June 5, 1979 to T. H. Ning et al. The Ning et al. patent discloses a method consisting of a sequence of process steps for fabricating a bipolar transistor having base contacts formed of polysilicon material and an emitter contact formed of polysilicon material or metal. The emitter contact is self-aligned to the base contacts by the use of process steps wherein a single mask aperture is used for defining the base contacts and the emitter.
Reference is made to U.S. Pat. No. 4,159,915 entitled "Method For Fabricating Vertical NPN and PNP Structures Utilizing Ion-Implantation" granted July 3, 1979 to N. G. Anantha et al. The Anantha et al patent discloses a method for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon insolated from one another by isolation regions. Buried regions are formed by overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP region is then implanted by suitable ion implantation techniques. A Schottky barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.
Reference is made to U.S. Pat. No. 4,160,991 entitled "High Performance Bipolar Device and Method for Making Same" granted July 10, 1979 to N. G. Anantha et al. The Anantha et al patent discloses a method for manufacturing a high performance bipolar device. The resulting structure has a very small emitter-base spacing. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.
The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power performance. The parameters that are essential to such high performance bipolar transistors are low parasitic capacitances as realized by (a) shallow vertical junction and (b) small horizontal geometry. To achieve these goals it is necessary to make the devices in the integrated circuits as small as possible.
With the advance in semiconductor processing technologies, such as in the fields of ion implantation, deep dielectric isolation, electron beam and x-ray lithography, reactive ion etching (RIE), advanced insulator and polysilicon deposition techniques, and metal lift-off processes, fabrication of the ultrahigh performance integrated circuit devices can be achieved.
Ion-implantation provides a means for precisely controlling the total amount of impurity transferred to the wafer. The impurity depth distribution is accurately controlled by implant energy. Unlike the conventional thermal diffusion process ion implantation is not a high temperature process. Thus, by using photoresist or metal masking, multiple impurity introduction operations can be achieved without resort to high temperatures. A final thermal drive-in diffusion is sufficient to anneal out the radiation damage caused by implantation, and obtain desired device junction depth. Consequently, integrated circuit devices can be made shallower, with greater precision of the impurity distribution using ion implantation technology.
As the semiconductor devices become shallower, it is desirable to reduce the overall junction area so as to reduce parasitic capacitance. Further reduction of device parasitic capacitance can be achieved by shrinking of device horizontal dimensions and using dielectric isolation. Dielectric isolation is a method of fabricating integrated circuits in which the device components are isolated by other than P-N junctions. A well known dielectric isolation namely, "Recessed Oxide Isolation" (ROI) is a commonly used process in present day semiconductor technology. Using Si.sub.3 N.sub.4 as the oxidation barrier, the ROI technique is done by etching grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The silicon exposed by the grooves is then thermally oxidized to form recessed oxide regions providing dielectric isolation. The problem associated with the ROI is the formation of "bird's head" and "bird's beak" structure at the lateral edges of recessed oxide. The "bird's head" is undesirable because it can cause breaks or discontinuities in thin films covering the steps. The indefiniteness of "bird's beak" structure reduces the available active surface area and, therefore, imposes the need for wider tolerance of lateral dimension in the integrated circuit layout. A newly developed oxide isolation called "Deep Dielectric Isolation" (DDI) avoids the above mentioned ROI problem. The DDI process utilizes reactive-ion etching (RIE) to form deep narrow trenches into the wafer surrounding those regions in which devices are to be formed. [Reference is made to U.S. Pat. No. 4,104,086, entitled "Method for Forming Isolated Regions of Silicon Utilizing Reactive Ion Etching" granted Aug. 1, 1978 to J. A. Bondur et al., and U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method for Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 to J. A. Bondur et al., respectively of common assignee with subject application]. The trenches are overfilled with SiO.sub.2 put down by chemical vapor deposition (CVD) technique. The overfilled SiO.sub.2 also planarizes the device surface. A blanket RIE back-etching to the semiconductor surface yield deep oxide isolation trenches. Unlike the bird's beak in ROI structure, sidewalls of the DDI structure are nearly vertical. The surface of DDI regions and the silicon where devices are to be formed are coplanar. With DDI, the doping process for various device regions is then self-aligned by oxide isolation. The self-aligned process eliminates precise mask alignment steps and also saves a number of mask steps in the device fabrication.
As mentioned above, DDI enables us to form devices with considerably smaller cell size than those formed by using either P-N isolation or by ROI. Further reduction of device horizontal dimension requires the use of high resolution capabilities of lithography and etching processes. The electron lithography is the most promising method for delineating submicron size device patterns. For device window opening, the reactive ion etching (RIE) is the most attractive alternative of the conventional wet solution etching. The RIE is a dry process having directional etching characteristics. The etched device windows preserve the lithography defined etch mask dimensions, and the openings have vertical sidewalls. Thus, the E-beam lithography and reactive ion etching are common for fabricating very small device geometries.
For the very small bipolar transistor devices, as for example, micron size transistors, the base areas and, therefore, the collector-base parasitic capacitance is the most significant performance parameter. In the bipolar transistor the active base area is the region below the emitter. In the conventional transistors, fabricated by prior art, the base contacts are formed above the inactive base area surrounding the emitter. The transistor base area that is needed to accommodate the emitter and base contacts is considerably larger than the active base area. To reduce the base area for making ultra high performance bipolar transistors, a different approach in making the base contact is desirable.